The only 3 things to remember

1. Speak slowly. Pause is power.

2. Land the number, then explain it.

3. "Great question — let me show you" is a complete answer.

If you blank on a number

Round it up and own it: "under 5 seconds", "tens of millions of transistors", "roughly 10× the throughput". Don't reach. Don't say "uhh".

If you blank on the EDA

Defer cleanly: "Allen is our application engineer for this — let me grab him in 2 minutes, or I'll send the precise answer tonight." That's professional, not weak.

Overview · Your two stage moments

Two awards. Two pitches. Same Aniah.

Both pitches are 5 minutes, English, slides allowed. Same proof-points. Different emotional spine.

Pitch A · Best AI Award (Bronze)

"We brought AI to the part of EDA nobody else could."

Audience: AI judges, AI/IC press, tech leaders. Want to hear how AI is real here.

Spine: Semantic engine reads the netlist with intent → MCP feeds Amigo → Amigo never hallucinates because it sees verified context → engineer trusts the fix.

Existing source deck: amigo-llm-taiwan.pptx (6 slides, IC_INTL-02). Use as backbone.

Stage: Wed Jun 3, 14:00–15:30 · Best AI Awards venue.

Pitch B · ICTGC (Batch 4 winner)

"We are the GPS for IC sign-off — and we're shipping today."

Audience: NSTC, TCA, NDC, semi ecosystem, foundry/design-services. Want product proof and Taiwan relevance.

Spine: Sign-off is the last 5% that burns 50% of the schedule → OneCheck finds errors in seconds → V4 demo shows it live → French AI-EDA challenger lands in Taiwan.

Existing source deck: OneCheck_Road_to_SignOff.pptx + your V4 demo. Use selectively.

Stage: Tue Jun 2, 15:00–18:00 · InnoVEX Center Stage (ICTGC ceremony).

⚠
One narrative across the week. Whatever you say on stage will be replayed at the booth, the gala, and the media interview Thursday. Keep the four headlines tight: (1) ERC is the sign-off bottleneck nobody fixed. (2) AI in EDA is digital P&R — analog ERC is our white space. (3) Shift-left in Virtuoso, no rule coding, 19M transistors in <5s. (4) Foundry-neutral European challenger, already shipping.
Pitch A · ~5 minutes · English · slides

Best AI Award — the Amigo story.

Built off your amigo-llm-taiwan.pptx. Six slides. Each block below = the slide + speaker notes + the exact words to say.

Spine: AI that doesn't hallucinate, because it doesn't read text — it reads a verified semantic model.
1 0:00 → 0:20 TITLE — Amigo-LLM
From months to days
Visual: existing title slide. Just stand. Smile. Don't rush.

Open · slow. Land your name and the prize.

15 seconds · slow · eye contact Good afternoon. — breathe — My name is Kevin Firaguay, I lead product at Aniah. pause 1 sec Thank you to the Best AI Awards committee for the bronze recognition — and to the AI community in Taiwan for giving us a stage to talk about what AI looks like inside a chip design tool.
iWhy this opening: "Kevin Firaguay" + "Aniah" pinned early so they remember you. Bronze acknowledgment shows confidence without arrogance.
2 0:20 → 1:00 What Aniah does
FASTER · SAFER · ERC-FOCUSED
Visual: existing 3-column slide. Look at the audience, not the slide.

Plant the problem with one sentence civilians understand.

40 seconds At Aniah, we help analog and mixed-signal chip designers reach the finish line — what the industry calls sign-off — without finding out the hard way that the design has an electrical bug. pause Today that last step takes months. We compress it to days. We do one thing — Electrical Rules Checking — and we've been building it for six years, deeply.
iTranslation key: "sign-off" = the moment a chip design is declared ready to manufacture. "ERC" = the test that checks the electrical wiring rules. Don't define those terms unless asked — just plant them.
3 1:00 → 2:00 Sign-off stalls — the last 5%
burns 50% of the schedule
Visual: the "5% / 50%" stat hits hardest. Stay on this slide a beat longer.

The bottleneck — make them feel it.

60 seconds · this is where you slow down Why does sign-off take so long? pause Because the verification step finds thousands of electrical violations, and humans have to read each one to decide: is it a real bug, or noise? — On a modern chip at advanced nodes, that triage burns the last 5% of the schedule — which somehow always becomes 50% of the calendar. long pause And if a single one is missed, that's a respin. Millions of dollars. Six more months of schedule. beat Now — here's the part everyone misses. AI in chip design today is mostly digital place-and-route. Nobody has brought AI to the analog side. Because analog reasoning requires understanding intent — not just text.
!The transition line at the bottom is your bridge into the next slide. Say "intent — not just text" and let the silence sit before clicking forward.
4 2:00 → 3:15 We built a semantic engine
It reads the netlist as the designer wrote it
Visual: input vs. captured-meaning diagram. Gesture left-to-right.

The technical claim — credibly, simply.

75 seconds · the proudest moment For six years, we built one thing: a semantic engine that reads a netlist — the raw electrical description of a chip — and rebuilds what the designer actually meant. pause It captures the power domains. The circuit topology. The role of every transistor. The assumptions the designer made when they drew it. beat That semantic model is the breakthrough. — It's why we can analyze 19 million transistors in under 5 seconds, deterministically, with no rule coding. pause And it's also why our AI assistant — we call it Amigo — doesn't make things up.
iThe two killer numbers to land cleanly: "six years" (depth) and "19 million transistors in under 5 seconds" (proof). Round-number them — never quote a decimal you can't defend.
5 3:15 → 4:30 Generic LLM vs Amigo-LLM
Plausibility vs proof
Visual: side-by-side comparison. Point to the contrast.

The AI differentiation — the slide that won bronze.

75 seconds · this is your bronze moment A generic LLM looking at a netlist sees a string of text. It guesses. It hallucinates a fix that looks right. In chip design, "looks right" is a respin. long pause Amigo is different — architecturally. — Amigo connects to the semantic model through an open protocol called MCP. pause So Amigo never reads raw netlist text. It reads verified circuit meaning. It knows the power domains. It knows the topology. pause When Amigo proposes a fix, the fix is validated against the model before the engineer ever sees it. beat That's the AI-EDA shift. Not a chatbot bolted on. An AI that reads silicon — and proves intent.
✓If the room is technical, add: "MCP — the Model Context Protocol — is the same open standard Anthropic published in late 2024. We were one of the first EDA tools to adopt it." That lands credibility instantly with AI engineers.
6 4:30 → 5:00 Validated with NVIDIA
LIVE DEMO / Thank you
Visual: NVIDIA validation card. Final smile + outstretched hand.

Close · with proof and an invitation.

30 seconds · land it Amigo is running today on production silicon, in direct collaboration with hardware teams at NVIDIA. pause Six years of analog engineering, six months of building Amigo on top — and a bronze tonight that means the world to a small French team a long way from home. — Thank you. beat Come see us at Booth S0724 — all week — and I'll show you Amigo live. pause Thank you, Taipei.
!If you have a live demo slot tagged on the stage agenda, replace "Come see us at Booth..." with "And — if I have one more minute — let me show you Amigo, live." Then drive the V4 demo (see demo flow).

What to do with the 30 seconds you'll likely have left

Option A — End early, smile, walk off

Best AI Awards expect crisp speeches. Ending 30s early reads as composed. Don't fill time with filler. Walk off at "Thank you, Taipei."

Option B — Add the 30-second demo teaser

"If the screen can show this — here's Amigo finding a power-domain violation in a real circuit, in three seconds. (click · point · click) Thirty seconds is enough for me to prove it. Thank you."

Pitch B · ~5 minutes · English · slides

ICTGC — the OneCheck demo story.

This is the ceremony pitch on Tue Jun 2 at InnoVEX Center Stage. Audience is the Taiwan semi ecosystem + ICTGC officials + press. Proof beats poetry here.

Variant A · LIVE V4 demo on stage Variant B · Recorded 60-sec video Decide on the day. Prep both.

Five-slide structure (drop-in)

1 0:00 → 0:30 Thanks · who we are
Aniah · ICTGC Batch 4
Visual: Aniah logo · ICTGC winner badge · "Grenoble → Taipei"
30 seconds Good afternoon. — I'm Kevin Firaguay, Product lead at Aniah. pause Aniah is a French AI-EDA company from Grenoble. We were named one of eleven winners out of two hundred and nine proposals from thirty-eight countries in the IC Taiwan Grand Challenge — Batch 4. — Thank you to NSTC, TCA, and NDC for trusting a European team with this honour. beat Today I'm going to show you what we built — and why it matters for Taiwan.
2 0:30 → 1:30 The bottleneck: sign-off
"Last 5% = 50% of the schedule"
Visual: schedule bar that turns red in the last 5%
60 seconds In analog and mixed-signal chip design, the hardest part isn't the design. It's the verification — proving that every transistor obeys the electrical rules. We call it ERC. pause Today's tools take days to run, surface thousands of violations, and leave senior engineers to triage by hand. — Over half of advanced-node respins trace back to mixed-signal electrical bugs that ERC should have caught. pause The last 5% of the schedule burns 50% of the calendar.
3 1:30 → 2:30 Our breakthrough
Semantic model + AI = errors found AND explained
Visual: simplified semantic-engine diagram from Pitch A slide 4. Reuse.
60 seconds We rebuilt ERC from scratch around two ideas. pause One — a semantic engine that doesn't just see transistors, it sees intent: power domains, topology, designer assumptions. 19 million transistors in under 5 seconds, with no rule coding. — Two — an AI assistant we call Amigo, that reads the semantic model — not raw text — so it doesn't hallucinate, and every fix it proposes is validated before you see it. pause Together, ERC moves from a two-day sign-off gate to a live design-stage check inside Cadence Virtuoso. Shift left — really.
4 2:30 → 4:15 PROOF — the demo
Live (Variant A) or video (Variant B)
Visual: switch the projector to your V4 / Pyrrha demo OR play the recorded mp4.

Variant A · LIVE V4 demo on stage (105 sec)

During the demo · narrate every click I'm switching to the live tool now. What you'll see is our V4 interface — the same engine, a redesigned UI. pause (click: log in auto) I'm signing in — done in a second. (click: open project) I'm opening a real customer block — about a million transistors. — (wait: wizard auto-advances) Watch the wizard configure itself — technologies, power domains, contention rules — all auto-derived from the netlist semantics. pause (click: Violations panel) Here are the errors — grouped by root cause — not by raw violation. Thousands collapse into dozens. — (click: a cluster) I click one. (click: Explain) I press Explain — Amigo streams the analysis in natural language. pause (point to Apply) And here — one click — Apply fix to N instances. That's the loop. Find, understand, fix — in seconds.
!Live demo break-glass. If the screen freezes or the worker disconnects: say "and exactly because chip designers don't want to deal with this, we made the recovery one-click — but for the sake of time, let me show you the recorded version" and switch to the video. Have it queued.

Variant B · Recorded 60-sec video (start at 2:30)

Over the video · talk in present tense Let me show you. What you're watching is the V4 interface running on a real customer block — about a million transistors. pause The tool signs in. The wizard auto-configures. pause The Violations panel groups thousands of raw findings into dozens of root causes. — I click a cluster. I press Explain — Amigo streams a natural-language analysis. pause One click — Apply fix to N instances. beat Find. Understand. Fix. In seconds.
5 4:15 → 5:00 Why Taiwan matters · thank you
Booth S0724 · all week
Visual: Taiwan + France handshake or Aniah team in front of booth
45 seconds Why does this matter for Taiwan? pause 90% of advanced semiconductors are designed or made on this island. Sign-off pain isn't a French problem or an American problem — it's a Taiwan problem first. — We are foundry-neutral. European. Already shipping to NVIDIA, STMicro, Prophesee, and pilots across the Hsinchu corridor. pause ICTGC has given us the runway to bring this here properly. We are returning the favour — pilots, recruiting at NYCU, a permanent office, a long bet on Taiwan. long pause Thank you, NSTC. Thank you, TCA. Thank you, Taipei. — Booth S0724, all week. Come find me.
✓Why these specific thanks: NSTC + TCA are ICTGC organizers; saying their names from the stage is protocol and earns goodwill. The "Taipei" close mirrors what Vincent would do — claims the city, not the country.
V4 / Pyrrha demo · the rehearsed click path

9 steps · 90 seconds · the muscle-memory demo.

Same demo for booth, stage, customer 1:1, gala primer. Practice this five times before Tuesday. The whole point is that you never have to look at the screen to know what's coming.

Pre-demo · 30 seconds before you start

Setup state: V4 frontend running at :24294 (Pyrrha) or :4290 (dev). Worker connected (top-right pill says CORE · <hash>). Amigo connected (pill says Amigo · ready). If either is "Connecting...", wait 10–20 sec — don't start.

If something is wrong: restart via the orchestrator (:4280) — or just say "let me show you the recorded version, the demo machine is being precious today" — never apologize twice.

1

Open V4 — auto-login

Browser opens at the V4 URL. Auto-logs in as root. The Violations page loads.

"This is V4 — our next-generation interface. I'm logging in as a designer."
2

Wizard auto-advances

Global config → Technologies → Powers → Contentions → Error reporting. Each step auto-fills from netlist semantics — designer doesn't write rules.

"Watch the setup — the tool reads the netlist and configures itself. No rule deck. No multi-day setup phase."
3

Configure panel (collapsible)

Briefly expand the Configure side panel: live ERC categories, technologies, power scenarios, netlists.

"For the engineers in the room — this is the live config. Every category is editable; defaults come from the PDK and the netlist."
4

Violations panel — per-type counts

Center column shows violations grouped by type (Missing Ls Up, Missing Ls Down, Contention, MIC, Conditional Leakage). Proportional bars.

"Thousands of raw violations. But our Smart Clustering already collapsed them into a handful of categories."
5

Click a cluster (e.g. "Missing Ls Up")

Right panel shows auto-populated short description + a reference diagram + cluster breakdown.

"I click one cluster. The tool shows me the schematic, the affected instances, and the electrical context."
6

Press "Explain" — Amigo streams

Amigo button at the top of the panel. Streams natural-language explanation in ~30 seconds. Trained on the semantic model, not raw text.

"This is Amigo — our AI assistant. It's not reading text — it's reading the semantic model through an open protocol called MCP. Watch it explain what this cluster means, in English."
7

Suggested Fix appears

Below the explanation: suggested fix card. Validated against the model — not invented.

"Notice that the fix is not 'something that looks plausible' — it's a fix that has been checked against the circuit semantics before it ever reaches the engineer."
8

"Apply to N instances" button

One click applies the fix across all instances of this root cause. Track which were modified vs waived.

"One click — apply to all 47 instances of this root cause. The designer is back to designing."
9

Close · the loop

Hand goes back to the audience.

"Find. Understand. Fix. In seconds — not weeks. This is the loop we sell."
!If a CAD engineer asks during the demo: "Can I see the rule deck?" — answer: "There isn't one. The semantic engine reasons over the netlist directly. PDK + power-domain definitions are the only inputs. We can show you the configuration JSON if you want." Then signal Allen.
Q&A bank · the four fear zones

The questions that scare you — answered.

Each entry: the question · the 30-second credible-PM answer you can deliver · the bridge phrase to defer if pushed deeper · what to absolutely NOT say.

FEAR 1  Deep EDA / ERC mechanics

How does your sign-off methodology compare to Calibre PERC?
Answer (30 sec)
We don't replace Calibre PERC — we relieve it. Calibre runs at sign-off, on rule decks that take months to maintain. OneCheck runs upstream — inside Cadence Virtuoso, at the design stage — and catches the structural electrical bugs in seconds, before the designer even submits to PERC. The result: when PERC eventually runs, there's almost nothing left to find. We shift the bottleneck out of the critical path.
Bridge if pressed
"That's an excellent foundry-methodology question — Allen, our application engineer, has the deep methodology answer. Let me grab him, or I can send a written response tonight if he's tied up."
Do NOT say
"We replace Calibre." (Untrue + insults Mentor/Siemens in the room.) Don't quote specific runtime ratios you can't back up.
Do you have a rule deck? What's the maintenance burden?
Answer (30 sec)
No rule deck. That's the architectural choice. Traditional ERC requires a rule deck per technology node, maintained by a CAD team for months per refresh. OneCheck reasons over the semantic model of the circuit directly. The only inputs are the PDK and the power-domain definitions — both of which the designer already has. So the maintenance burden is essentially zero per project.
Bridge if pressed
"On exactly which classes of checks are captured without a rule deck — Allen can walk you through the error catalog. We support Contention, Conditional Leakage, MIC, and the standard cross-domain checks today."
What's your foundry qualification status? Are you on TSMC's reference list?
Answer (30 sec)
We're foundry-neutral by architecture — we don't depend on a foundry-specific rule deck. We work today on TSMC, GlobalFoundries, and STMicroelectronics technologies because our customers ship on those nodes. Formal reference-list inclusion is a 2026 conversation — that's one reason we're sitting with Daw Hsu, who spent 30 years supporting TSMC, this week.
Bridge if pressed
"For the exact PDK validation matrix — let me put you in touch with Allen. I want to make sure I give you a precise list, not an approximate one."
Do NOT say
"We're on the TSMC reference list." (We're not — yet.) Don't promise timing on foundry qualification.
How do you handle regressions across design revisions?
Answer (30 sec)
OneCheck supports incremental re-verification — when the netlist changes, we re-analyze only the affected regions. On the roadmap, we have a Change Tracker that snapshots semantic-model state per revision, so engineers see exactly which violations are new, which are unchanged, and which were closed. That's the "Road to Sign-Off" framing — readiness score instead of pass/fail.
Bridge if pressed
"The current incremental flow is in production. The Change Tracker is on the near-term roadmap. Happy to walk through the timing with Allen."

FEAR 2  Analog / mixed-signal circuit-level

How do you handle level shifters and isolation cells?
Answer (30 sec)
Level shifters and isolation cells are part of our standard topology library — we recognize them, model their behavior, and reason about the crossings they enable. The whole point of our power-domain analysis is exactly this: identifying where a level shifter is required, where one is missing, and where one is present but mis-oriented. That's a primary class of check we deliver out of the box.
Bridge if pressed (e.g. exotic topology)
"On that specific topology — let me have Allen confirm whether it's covered today or scheduled. I don't want to overclaim."
What about ESD checks? Floating gates? Current mirrors?
Answer (30 sec)
Yes — these are in our error catalog. We model standard ESD structures, detect floating gates, and recognize current mirrors as electrical topologies. Our SysCon engine — the system-conditional analysis — is what makes us strong on these: it tracks which paths are active under which conditions, so we don't false-positive on mirrors that are correctly enabled in their operating mode.
Bridge if pressed
"For the specific ESD network you have in mind — Allen can show you the exact check on a real example. Want me to schedule that demo with him this week?"
How do you handle complex power scenarios — PWM, sleep modes, multi-rail?
Answer (30 sec)
We have a feature called the Power Matrix — power scenarios can be defined as tables, per-instance, or as power functions with aliases. PWM dimming, sleep modes, multi-rail, mission profiles — all expressible. That's actually one of our strongest fits with automotive DDIC customers like Novatek, where AEC-Q100 reliability checks need conditional power awareness.
Bridge if pressed
"Let me show you the Power Matrix UI — it's much clearer than describing it. Allen and I can set up a 30-minute deep dive."
How do you avoid false positives on analog circuits?
Answer (30 sec)
Two ways. One — the semantic engine reads topology, so a transistor doing analog work isn't checked with digital assumptions. Two — our SysCon system tracks which conditions activate which paths, so violations that exist only under impossible conditions are filtered out automatically. The Smart Clustering layer further groups true positives by root cause, so engineers see ~20 issues to triage instead of 2,000.
Bridge if pressed
"On a specific false-positive pattern from your design — Allen can run it through OneCheck this week and walk you through the result. I'd rather show than tell."

FEAR 3  Sign-off / "Road to Sign-Off" claims

When you say "road to sign-off" — do you actually sign off the design?
Answer (30 sec) · the defensible version
No — we don't replace sign-off. We make sign-off faster and safer. Foundry sign-off methodology stays where it is (Calibre PERC, IC Validator, etc.). What we do is take the upstream burden — the structural electrical checks that currently absorb 50% of the calendar — and compress them into a design-stage flow. Engineers reach sign-off with a clean design, not with thousands of last-minute violations. That's the "helper-to-sign-off" positioning.
Bridge if pressed (e.g. "but what about regression sign-off?")
"Sign-off methodology is a deep topic — every customer has a slightly different one. Allen and I prefer to walk through your specific flow before claiming where exactly we add value. Want to set up that conversation?"
Do NOT say
"We sign off your design." (We don't — and overclaiming will cost credibility with the CAD engineers in the room.) Don't quote a specific percentage of sign-off time saved unless you have a customer case-study number from Allen.
What's your readiness-score model? Is it audited?
Answer (30 sec)
The readiness score is a composite across six axes — ERC checks passed, violation triage status, root-cause identification, waiver validity, regression status, block sign-off lock. Today the score covers ERC; the architecture is extensible to DRC and LVS through ingestion from other tools. It's a methodology view, not a foundry certification — it gives engineers a "how close am I to sign-off-ready" number instead of "pass/fail today".
Bridge if pressed
"The axis weighting per customer is something Allen can walk you through with our methodology playbook — happy to set up that conversation."

FEAR 4  Hard commercial questions

What does OneCheck cost? What does a deployment look like?
Answer (30 sec)
Pricing is per-seat per year, structured around the size of the design team and the number of foundry technologies. I'd rather scope it to your actual usage than quote a list price that won't be relevant. POCs are typically free for a defined scope — one block, one technology, agreed success criteria — and convert to paid deployment if the POC clears.
Bridge if pressed for a number
"For an exact quote — let me put Allen in touch with you Monday. I want him to scope correctly rather than me guessing a number on a stage."
Do NOT say
A specific dollar number. A "starts at $X" anchor. Don't promise free perpetual licenses.
Is NVIDIA a customer? Are they paying?
Answer (30 sec) · respect the do-not-claim line
NVIDIA design and verification teams are running OneCheck on production silicon blocks today, in direct collaboration with our team. That's the most I'm allowed to say publicly — out of respect for our customer relationships. The fact that Eric Hsu flew from the US for this week, and that there's an NVIDIA HQ workshop on June 10, is probably the more useful signal.
Bridge if pressed
"On commercial specifics — that's a conversation we keep customer-direct. Happy to introduce you to references that have agreed to speak publicly, like STMicro or Prophesee."
Do NOT say
"NVIDIA is a paying customer." (Even if true in some form — we have public guidance not to logo-drop.) Don't name NVIDIA people from the stage.
How are you different from Insight Analyzer (Siemens) or IC Validator PERC (Synopsys)?
Answer (30 sec)
Insight Analyzer — which Siemens acquired in 2023 — is our closest architectural competitor; they're a real team and we respect them. Two differences in our positioning: (1) we live inside Cadence Virtuoso at the design stage — shift-left rather than sign-off-gate; (2) our AI layer, Amigo, runs over a semantic model via MCP, so it explains and validates fixes — not just flags violations. Synopsys ICV PERC remains the foundry sign-off reference; we're not trying to displace that role.
Bridge if pressed
"On a feature-by-feature comparison — Allen has the matrix. I'd rather give you the precise version than improvise."
Do NOT say
"We're better than Insight." (Daniel Lin and Nina Lin from Siemens are AT the gala. Tone matters.) Don't denigrate Synopsys — Nasser Lin from Synopsys is also at the gala.
How many people are at Aniah? What's your runway?
Answer (30 sec)
We're a focused team in Grenoble, France, deep on analog ERC for six years. Series A from Supernova Invest and Bpifrance — well-capitalized for the European deep-tech profile. ISO 9001 and ISO 27001:2022 certified, which matters for enterprise procurement. We are scaling the Taipei presence in 2026 — that's part of why we're here.
Bridge if pressed on headcount
"Exact headcount and runway numbers I'd rather share in a 1:1 with our CEO Vincent — he can connect by video next week if helpful."
Bridge phrases · when Allen isn't in the room

Five ways to defer gracefully.

Memorize these. They turn "I don't know" into "I am being professional."

1 · Allen, soon

"Allen is our application engineer for that depth of technical question — he's at the booth right now, let me bring him over in two minutes."

2 · Allen, tonight

"Allen has the precise answer. He's tied up at another conversation — I'll text him to send you a written response tonight. What's the best email?"

3 · CEO escalation

"That's a CEO-level question — Vincent isn't here this week, but I can set up a video conversation for next Monday."

4 · Demo, not words

"This is the kind of thing easier to show than describe. Can I run it through OneCheck on a real example this week? Want to send me a block?"

5 · Honest, narrow

"I'm the product lead, not the application engineer — I want to give you the precise answer, not an approximate one. Let me come back to you within 24 hours with the right depth."

6 · Reverse the question

"Before I answer — can I ask what's behind the question? If you're scoping a POC, the answer depends on which technology and which block class — I want to give you something useful."
✓Tone discipline: never start with "I don't know" — start with the bridge. Engineers respect "I want to give you the precise answer" more than they respect "I think it's around 30%". You're a product lead, not the AE — that's allowed, that's expected.
Flashcards · the numbers you must own

If you remember nothing else — remember these.

19Mtransistors analyzedin under 5 seconds
<5sanalysis runtimevs days for incumbent
~1000×speed vs PERCuse as "orders of magnitude"
50%+of advanced-node respinsare mixed-signal driven
5%/50%last 5% = 50% calendarsign-off bottleneck framing
6 yrsbuilding semantic ERCdepth, not buzzword
11/209ICTGC Batch 4 winnersfrom 38 countries
BronzeBest AI Award 2026International IC Design · IC_INTL-02
5NVIDIA seats at gala5 functions, 1 keystone account
20curated gala guests2 Aniah tables, 3.5 hours
S0724booth numberICTGC Pavilion, Jun 2-5
ISO 27001:2022 certifiedLSTI, Sept 2025
!Rounding rules: always round UP for performance ("under 5 seconds", not "4.7 seconds"). Always round DOWN for claims ("over 50%", not "around 60%"). Defensible > impressive.
Booth + Gala · 5-minute conversation cards

Opening lines that work, by stakeholder type.

NVIDIA · designer / verification engineer

Gabriel Lee, Venser Wang, Yoyo Wu

"What's the part of your week you wish someone would just take off your plate?"
Are you on a Mixed-Signal SVE block? Where does ERC currently fit in your flow?

They're the daily users. Show them V4. Focus on triage time and false-positive rate. Don't pitch — listen.

NVIDIA · CAD engineer (EricH)

Eric Hsu — EDA kingpin

"You flew from the US for this — I owe you an honest read of where we are technically. Want me to start with the architecture, or the limits?"
What does the 6/10 HQ workshop need to land for it to move forward? Can we ship a scoping doc by Jun 17?

EricH is the make-or-break account. Be technical, be honest about limits, and let him drive.

MediaTek

Xavier / Nicky Liang

"We're not here to replace Calibre PERC. We're here to make sure you don't run it ten times before it passes."
What's blocking an upstream methodology pilot? Is Benjamin Chiu the right internal door for the conversation?

MediaTek is the public Calibre PERC reference customer — DON'T pitch replacement. Pitch shift-left + Virtuoso.

Novatek

Pete / Chunpo

"OLED TDDI and automotive DDIC — that's exactly the cross-domain HV/LV territory OneCheck was built for."
Could a single-IP POC on a DDIC block — with a Display Week 2027 joint paper — work for you?
Realtek (CSO)

Wed 6/3 1:1 · gala continues it

"The SerDes PHY noise into analog story — that's the wedge. May I scope a block POC with you?"
Where in your high-speed networking flow does ERC currently bottleneck?
Alcyon Photonics · Shake Chang

Co-packaged optics is open white-space

"Driver-CMOS to photonic-die crossings — nobody else is talking about ERC there. We'd love to write the first joint research note with you."
Are you the right tech lead, or should we involve someone on the photonic side first?
Siemens · Daniel Lin / Nina Lin

Partner-this-week, competitor-next-year

"You and Mentor own sign-off. We're complementary at the design stage. May I send Vincent for an exploratory call next week?"
Where do you see referral overlap? Could we co-sell in accounts where Calibre runtime is the bottleneck?

Critical: never put Siemens and Synopsys next to each other in seating or in conversation.

Synopsys · Nasser Lin

Senior R&D Director · they know ERC is hot

"ICV PERC for TSMC N2P full-path ESD — congratulations on that. We solve the upstream half. Can we explore a Virtuoso-to-ICV handoff story?"
If we send a clean design into ICV, does that reduce your support-call volume? Could that be a co-marketing story?
Leafy Lab · Ariel Yeh

Co-ICTGC winner · agentic AI for silicon

"You orchestrate verification flows. We're the highest-yield ERC primitive your agents could invoke. Can we draft an LOI before end of June?"
What's your nearest joint Asia GTM moment in 2H 2026?
NDC · Dr. Fang-guan Jan

Deputy Minister · Asia Silicon Valley 3.0

"We're a French team committing to a permanent Taipei presence. What does formal recognition under Asia Silicon Valley 3.0 look like?"
Could we be included in the next Taiwan-Europe semiconductor delegation?
NYCU · Dr. Charles Wen

Distinguished Professor · ASVA consultant

"NYCU is the feeder school. We'd love to sponsor a curriculum module on AI-driven ERC, and open the door to your students for internships."
What format of partnership has worked best for industry-academia AI initiatives at NYCU?
Daw Hsu (consultant, ex-Synopsys AE)

30 years TSMC support · gold

"Daw — your TSMC backchannel is what we most need to unlock. Can we scope foundry rule-deck pull-through together over the next 60 days?"
Where in the TSMC sign-off methodology playbook would you place OneCheck for inclusion?
i5-minute table conversation structure (every gala guest): 1 minute "thank you for being here, what brought you" · 2 minutes their context + their pain · 1 minute your single hook tailored to them · 1 minute "can I follow up next week, what's the right channel?" Walk away with the email, not the deal.
Things to NEVER say

The list of "don't, even if it feels right."

On stage · on social · at the booth · in the press interview

  • "NVIDIA is our customer." Say "running on production silicon in direct collaboration with hardware teams". Same truth, allowed framing.
  • Name customer companies as endorsers (NVIDIA, MediaTek, Novatek, Realtek). They're guests, not endorsers. Public references = STMicro, Prophesee only.
  • "We replace Calibre." We don't. Say "we relieve Calibre" or "shift-left, before PERC".
  • "We sign off your design." We're a helper to sign-off. Say "we make sign-off faster and safer" — never "we do sign-off".
  • A specific dollar number. Pricing is conversation, not announcement.
  • "We're better than Insight Analyzer." Daniel Lin, Nina Lin, Nasser Lin are at the gala. Tone: complementary, not combative.
  • "Huge announcement coming." Don't tease — land specifics or skip.
  • The names of the consultants Benjamin Chiu / Daw Hsu publicly. They are working with us — that's not for the stage.
  • Internal headcount, runway, deal size numbers on stage. CEO-level questions deferred to Vincent.
  • Decimal numbers you can't defend ("4.7 seconds", "62.3% reduction"). Round-numbers only.
  • Disparaging the audience's existing tools in front of them. "Calibre is slow" said to MediaTek = lost trust.
!If you slip up: don't correct yourself awkwardly in the moment. Move on. Allen / I can clean it up afterward in any follow-up. Visible self-correction draws more attention than the original slip.
If everything breaks — the emergency kit

You will be fine. Here's how to recover from anything.

Projector fails / no slides

What to say (out loud, calm):

"The slides aren't going to make me — and they shouldn't make this story. Let me tell you in 90 seconds why we're here. (pause) I'm Kevin from Aniah. We're a French AI-EDA team. ICTGC named us one of eleven winners from 209 proposals. We do one thing: we shrink the last 50% of the chip-design calendar — the verification step — from days to seconds. We do it with a semantic engine that captures what the designer meant, and an AI assistant called Amigo that explains errors and proposes fixes without hallucinating. (pause) Come to Booth S0724 and I'll show you on my laptop."

V4 demo crashes mid-pitch

Don't apologize twice. Say once: "This is why we're polishing V4 for full launch — let me switch to the recorded version" — switch to the mp4 — and narrate over it (use the Variant B script from Pitch B slide 4).

Restart path if needed: orchestrator GUI at :4280, "Start all" button, wait 10–20 sec for worker to register. Then say "we're back — and here's exactly where we were heading..."

You blank mid-sentence

Default recovery line: "Let me say that again, more simply." Then restart the sentence from a known anchor (one of the headlines). Audience reads that as care, not as failure.

Worst case: drink water. The pause gives you 5 seconds. Then pick up from your next slide title.

A question you have no idea how to answer

The universal answer: "That's a great question — and exactly the kind of question I want to give you a precise answer to, not an approximate one. Let me come back to you within 24 hours." Take their email. Move on.

Never say "I don't know." Always say "I want to give you the precise answer."

A hostile / aggressive question

Don't match the temperature. Say slower: "I hear the question — let me make sure I understand what's behind it. Are you asking about [X] or [Y]?" Reframing buys time and shifts power.

You're late / over time

If 1 min over: cut to the close, smile, walk off — never apologize. If 2 min over: the moderator will signal — accept it, finish the sentence, "thank you", walk off.

Pre-stage · the 60-second checklist

Run this BEFORE you walk on stage. Every time.

Body · 30 seconds

  • Three slow breaths — in for 4 counts, hold 4, out for 6. Drops cortisol immediately.
  • Roll shoulders back, plant feet. Posture before words.
  • Smile — even forced. Tricks your nervous system into "I'm safe here."
  • Drink water. Cotton mouth kills the first sentence.
  • Mic placement check. Lapel = below collarbone, not on the necktie.

Mind · 30 seconds

  • Say your opening sentence aloud, even silently. Anchors muscle memory.
  • Look for one friendly face in the audience. You'll come back to that face when you wobble.
  • Remind yourself: you've won. Bronze AI award. ICTGC top-11. The hard part is done.
  • The audience wants you to do well. Nobody is there to see you fail.
  • If anything goes wrong, you have the emergency kit.
★The single most useful thing you can do in the 60 seconds before walking on stage: speak the FIRST 10 WORDS of your pitch out loud to yourself, slowly. "Good afternoon. My name is Kevin Firaguay, I lead product at Aniah." Once your mouth has said that out loud, your body knows it can do it on stage.

Pre-stage logistics checklist (Mon Jun 1 evening)

You're not selling a product. You're telling a six-year story to a room that wants you to win. The bronze is already on the shelf. The ICTGC win is already in the bag. Everything from here is upside.

Cockpit v1 · for Kevin · Taiwan COMPUTEX week, June 1–5 2026. Iterate freely.